Semiconductor processors continue to strive to reduce the size of individual electrical components, thereby enabling smaller and denser integrated circuitry. One typical device is a field-effect transistor. Such typically includes opposing semiconductive source/drain regions of one conductivity type having a semiconductive channel region of opposite conductivity type therebetween. A gate construction is received over the channel region. Current can be caused to flow between the source/drain regions through the channel region by applying a suitable voltage to the gate.
The channel region is in some cases composed of background doped bulk semiconductive substrate or well material, which is also received immediately beneath the opposite type doped source/drain regions. This results in a parasitic capacitance developing between the bulk substrate/well and the source/drain regions. This can adversely affect speed and device operation, and becomes an increasingly adverse factor as device dimensions continue to decrease.
Field-effect transistors have been described having channel regions formed separately from the source/drain regions. Such separate formation can result in a grain boundary between the source/drain regions and the channel region, which can produce a junction leakage problem when the grain boundary crosses the source/drain junction.
For the reasons stated above, and for other reasons stated below that will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternative methods for producing field-effect transistors, and their resulting devices.